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1 characteristics subject to change without notice 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary ?summit microelectronics, inc., 2001 ? 300 orchard city dr., suite 131 ? campbell, ca 95008 ? phone 408-378-6461 ? fax 408-378-6586 ? www.summitmicro.com ! ! ! ! ! ipmi implementation " " " " " ipmb interface " " " " " software controlled power-up/-down " " " " " status reporting: 5v, 3.3v, v1, v2, healthy, signal valid, reset " " " " " 2k-bit e 2 prom memory ! ! ! ! ! full voltage control for hot swap applications " " " " " detect, monitors and controls up to 4 inde- pendent supplies ! ! ! ! ! 14v high side driver generation allows use of low on resistance n-channel fets compact pci hot-swap controller with ipmi support features simplified application drawing ! ! ! ! ! under-voltage lockout ! ! ! ! ! electronic circuit breakers " " " " " programmable over-current levels ! ! ! ! ! card insertion detection ! ! ! ! ! card voltage sequencing ! ! ! ! ! flexible reset control " " " " " low voltage resets " " " " " host reset filtering " " " " " soft reset ! ! ! ! ! adjustable power on slew rate simplified application drawing triple voltage hot swap (12v, 5v, 3.3v) 1n4148 vcc hst_ 3v_mon card_3v_mon card_5v_mon sgnl_vld# healthy# drvren# vgate5 vgate3 gnd bd_sel2# bd_sel1# monitor1 monitor 2 cbi_3 cbi_5 local_pci_rst SMH4044 12v 5v 3.3v 10 ? 4.7k ? 0.33f 330k ? 0.1f 12v 5v 3.3v compactpci backplane 2057 sad-a ipmb_sda ipmb_scl gao ga1 ga2 sda scl a0 a1 a2 26 27 42 44 7 11 41 6 12 20 16 15 18 19 35 36 30 29 33 34 40 45
2 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary simplified application drawing triple voltage hot swap (5v, 3.3v, 1.8v) description the SMH4044 is a fully integrated hot swap controller that provides complete power control for add-in cards ranging in use for basic hot swap systems to high availability systems. it detects proper insertion of the card and senses valid supply voltage levels at the backplane. utilizing external low on-resistance n-channel mos- fets, card power is ramped by two high-side driver outputs that are slew-rate limited at 250v/s. the SMH4044 continuously monitors the host supplies, the add-in card supplies and the add-in card currents. if the SMH4044 detects the current is higher than the programmed value it will shut down the mosfets and issue a fault status to the host. the internal 256 8 e 2 prom can be used as configura- tion memory for the individual card or as general purpose memory. programming of configuration, control and calibration values by the user can be simplified with the interface adapter and windows gui software obtainable from summit microelectronics. vcc hst_3v_mon card_3v_mon card_5v_mon sgnl_vld# healthy# vgate5 vgate3 gnd bd_sel2# bd_sel1# monitor1 monitor 2 cbi_3 cbi_5 local_pci_rst SMH4044 1.8v 5v 3.3v 1.8v 5v 3.3v compactpci backplane 2057 sad-b 42 44 41 6 20 16 15 18 19 35 36 30 29 33 34 40
3 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary simplified application drawing hot swap with pup ldo sensing vcc hst_3v_mon card_3v_mon card_5v_mon sgnl_vld# healthy# vgate5 vgate3 gnd bd_sel2# bd_sel1# monitor 2 cbi_3 cbi_5 local_pci_rst SMH4044 5v 3.3v 5v 3.3v compactpci backplane 2057 sad-c monitor 1 ldo ldo 2.8v 1.8v 42 44 41 6 20 16 15 18 19 35 36 30 29 33 34 40
4 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary functional block diagram a0 a1 a2 scl sda pwr_en + ? vcc hst_3v_mon + ? card_3v_mon card_5v_mon local_pci_rst local_pci_rst# islew sgnl_vld# healthy# drvren# fault# vgate5 vgate3 1vref gnd bd_sel2# bd_sel1# 2.65v 2.80v 2.95v 3.10v 4.625v 4.375v + ? + ? pci_rst# + ? monitor1 monitor 2 + ? 1.25v 1.25v vsel reset controller 25ms 50ms 100ms 200ms 3.2s 1.6s 0.8s off watchdog timer cs# i 2 c interface + ? cbi_3 cbi_5 + ? 25mv 50mv 75mv 125mv 25mv 50mv 75mv 125mv charge pump slew rate controller control register status register 4k e 2 prom 16 15 4 33 30 21 40 6 7 11 12 27 26 32 29 8 20 19 45 1 2 34 41 36 44 46 3 18 42 35 bandgap control logic 2057 bd 25ms 50ms 100ms 200ms programmable functions
5 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary pin configuration pin descriptions a0, a1, a2 (7, 11, 12) address inputs 0, 1 and 2 are used to set the three-bit device address of the memory array. the state of these inputs will determine the device address for the memory if it is on a two-wire bus with multiple memories with the same device type identifier. scl (27) the scl input is used to clock data into and out of the memory array. in the write mode, data must remain stable while scl is high. in the read mode, data is clocked out on the falling edge of scl. sda (26) the sda pin is a bidirectional pin used to transfer data into and out of the SMH4044. data changing from one state to the other may occur only when scl is low, except when generating start or stop conditions. sda is an open-drain output and may be wire-ored with any num- ber of open-drain outputs. card_3v_mon (33) this input monitors the card-side 3.3v supply. if the input falls below v trip then the healthy# and sgnl_vld# outputs are de-asserted and the reset outputs are driven active. card_5v_mon (40) this input monitors the card-side 5v supply. if the input falls below v trip then the healthy# and sgnl_vld# outputs are de-asserted and the reset outputs are driven active. cbi_3 (36) cbi_3 is the circuit breaker input for the low supply. with a series resistor placed in the supply path between hst_3v_mon and cbi_3, the circuit breaker will trip whenever the voltage across the resistor exceeds 50mv. fault# 1vref vsel pwr_en nc monitor 1 a0 local_pci_rst# nc nc a1 a2 cbi_3 hst_3v_mon vgate3 card_3v_mon cs# nc monitor 2 local_pci_rst nc scl sda nc nc nc bd_sel2# bd_sel1# nc gnd healthy# sgnl_vld# pci_rst# nc nc nc nc nc islew drvren# cbi_5 nc vcc vgate5 card_5v_mon nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 2057 pcon
6 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary cbi_5 (44) cbi_5 is the circuit breaker input for the supply voltage. with a series resistor placed in the supply path between the 5v early power and cbi_5, the circuit breaker will trip whenever the voltage across the resistor exceeds 50mv. hst_3v_mon (35) this input monitors the host 3.3v supply and it is used as a reference for the circuit breaker comparator. if vcc3 falls below v trip then sgnl_vld# is de-asserted, the high side drivers are disabled, and local_pci_rst# is asserted. islew (46) a diode-connected nfet input. it may be used to adjust the 250v/s default slew rate of the high-side driver outputs. pci_rst# (21) a ttl level reset input signal from the host interface. a high to low transition (held low longer than 40ns) will initiate a reset sequence. the local_pci_rst# and local_pci_rst outputs will be driven active for a minimum period of t purst . if the pci_rst# input is still held low after t purst times out the reset outputs will continue to be driven until pci_rst# is released. pwr_en (4) a ttl level input that allows the host to enable or disable the power to the individual card. during initial power up this signal would start in a low state, and then be driven high during software initialization. if this signal is driven low then the power supply control outputs will be driven into the inactive state and the reset signals asserted. in a non-high availability system this input can be tied high. the pwr_en input is also used to reset the SMH4044 circuit breakers. after an over-current condition is detected the vgate outputs can be turned back on by first taking pwr_en low then returning it high. vsel (3) a ttl level input used to determine which of the host power supply inputs will be monitored for valid voltage and reset generation. this is a static input and the pin should be tied to v cc or ground through a resistor. vsel is high for 3.3v power, and low for 5v or mixed mode power. v cc (42) the power supply input. it is monitored for power integrity. if it falls below the 5v sense threshold (v trip ) and the vsel input is low then the sgnl_vld# and healthy# signals are de-asserted, the high side drivers disabled, and reset outputs asserted. on a compactpci board this must be connected to early power. gnd (18) power supply return line. ground should be applied at the same time as early power. bd_sel1#, bd_sel2# (16, 15) these are active low ttl level inputs with internal pull- ups to v cc . when pulled low they indicate full board insertion. on the host side the signals should be directly tied to ground. in a high availability application these inputs can be the last pins to mate with the backplane. alternatively, they can be actively driven by the host, or be connected to switches interfaced to the board ejectors, or any combination. both inputs must be low before the SMH4044 will begin to turn on the card side voltage. drvren# (45) an open-drain, active-low output that indicates the status of the 3v and 5v high side driver outputs (vgate5 and vgate3). this signal may also be used as a switching signal for the 12v supply. fault# (1) an open-drain, active-low output. it will be driven low whenever an over-current condition is detected. it will be reset when the pwr_en signal is brought low. healthy# (19) an open-drain, active-low output indicating card side power inputs are above their reset trip levels. local_pci_rst# (8) an open-drain active-low output. it is used to reset the card side circuitry on the add-in card. it is active whenever the card-side monitor inputs are below their respective v trip levels. it may also be driven low by a low input on the pci_rst# pin.
7 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary * comment stresses listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. temperature under bias ...................... C55c to 125c storage temperature ........................... C65c to 150c lead solder temperature (10 secs) .................. 300 c terminal voltage with respect to gnd: v 0 , v 1 , v 2 , and v 3 .......... C0.3v to 6.0v all others ...................... C0.3v to 6.0v absolute maximum ratings* recommended operating conditions temperature C40 o c to 85 o c. voltage 2.7v to 5.5v local_pci_rst (29) an open-drain (pfet) active-high output. it operates together with with local_pci_rst#, providing an ac- tive high reset signal which is required by many 8051 style mcus. it is active whenever the card-side monitor inputs are below their respective v trip levels. it may also be driven active by a low input on the pci_rst# pin. sgnl_vld# (20) an open-drain, active-low output that indicates card side power is valid and the internal card side pci_rst# timer has timed out. vgate3 (34) a slew rate limited high side driver output for the 3.3v external power fet gate. the output-voltage is generated by an on-board charge pump. vgate5 (41) a slew rate limited high side driver output for the 5v external power fet gate. the output voltage is generated by an on-board charge pump. 1v ref (2) this output provides a 1v reference for pre-charging the bus signal pins. implementing a simple unity gain amplifier circuit will allow pre-charging a large number of pins. monitor1, monitor2 (6, 30) voltage sensor inputs which will detect voltages and compare them to the internal 1.25v reference. the sensors can be independently configured to sense over voltage or under voltage and can be used as either host side voltage sensors or card side voltage sensors. cs# (32) an active low chip select input. this signal must be asserted during i 2 c communications. the cs# signal allows external decoding to be used to extend the number of SMH4044 devices on the same serial bus from 8 using the address inputs to an unlimited number. bus capacitive and resistance loading must be considered when using multiple i 2 c devices on the same bus. please refer to generic i 2 c documentation ("bus interface") in this data sheet for further information.
8 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary dc operating characteristics ( over recommended operating conditions; voltages are relative to gnd ) 2057 elect table l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u v c c e g a t l o v g n i t a r e p oy l n o t e s e r d i l a v r o f1 v i 1 c c ) g n i t a r e p o ( t n e r r u c y l p p u s 1a m i 2 c c g n i t i r w ( t n e r r u c y l p p u s 3a m v p i r t v p i r t v ( s l e v e l d l o h s e r h t 5 c c ) n o i t a r u g i f n o c v 5 2 6 . 40 5 . 45 2 6 . 45 7 . 4v n o i t a r u g i f n o c v 5 7 3 . 45 2 . 45 7 3 . 40 5 . 4v v p i r t v ( s l e v e l d l o h s e r h t 3 c c ) n o i t a r u g i f n o c v 0 1 . 32 0 . 30 1 . 37 1 . 3v n o i t a r u g i f n o c v 5 9 . 27 8 . 25 9 . 22 0 . 3v n o i t a r u g i f n o c v 0 8 . 22 7 . 20 8 . 27 8 . 2v n o i t a r u g i f n o c v 5 6 . 27 5 . 25 6 . 22 7 . 2v n o m _ v 5 _ d r a c n o i t a r u g i f n o c v m 0 5 v 5 c c + p i r t v m 0 5 v n o i t a r u g i f n o c v m 0 5 ? v 5 c c ? p i r t v m 0 5 v n o m _ v 3 _ d r a c n o i t a r u g i f n o c v m 0 5 v 3 c c + p i r t v m 0 5 v n o i t a r u g i f n o c v m 0 5 ? v 3 c c ? p i r t v m 0 5 v 2 r o t i n o m , 1 r o t i n o m2 . 15 2 . 13 . 1v v t s h r t s i s e r e t s y h t n i o p p i r t 0 2v m i i l t n e r r u c e g a k a e l t u p n i 2a i o l t n e r r u c e g a k a e l t u p t u o 1a v l i e g a t l o v w o l t u p n i1 . 0 ? 8 . 0v v h i e g a t l o v h g i h t u p n i2v c c v 1 +v v l o e g a t l o v w o l t u p t u ov c c i , v 5 = l o a m 1 . 2 =4 . 0v v h o e g a t l o v h g i h t u p t u ov c c i , v 5 = h o a 0 0 4 ? =4 . 2v v s r l o t u p t u o # t e s e r _ i c p _ l a c o l e g a t l o v w o l i l o a m 2 . 3 =4 . 0v v s r h o e g a t l o v h g i h t u p t u o t e s e ri h o a 0 0 8 = v 5 c c ? v 5 7 . 0 v v s r h o t u p t u o 5 e t a g v , 3 e t a g v e g a t l o v i h o a 0 2 =2 14 15 1v f e r v 1e g a t l o v t u p t u o e c n e r e f e rd a o l o n5 9 . 00 0 . 15 0 . 1v v b c e g a t l o v p i r t r e k a e r b t i u c r i c (v c c 5 _ i b c ? r o ) n o m _ v 3 _ t s h (5 _ i b c ? ) n o i t a r u g i f n o c v m 5 2 10 0 15 2 10 5 1v m n o i t a r u g i f n o c v m 5 70 65 70 9v m n o i t a r u g i f n o c v m 0 50 40 50 6v m n o i t a r u g i f n o c v m 5 20 25 20 3v m
9 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary device operation power up sequence the SMH4044 is an integrated power controller for any hot swappable add-in card. it provides all the signals and control functions to be compatible with compactpci hot swap requirements for basic hot swap systems, full hot swap boards, and high availability systems. insertion process as the add-in board is inserted into the backplane, physical connections are made with the chassis in order to properly discharge any voltage potentials to ground. the board will first contact the long pins on the backplane that provide early power (5v, 3.3v and ground). depend- ing upon the board configuration, early power and ground should be routed to the SMH4044. as soon as power is applied the SMH4044 will assert the reset outputs to the card side circuits, turn off the vgate3 and vgate5 outputs (disabling the external power fets) and assert 1vref. this signal can be used to pre-charge the i/o pins before they begin to mate with the bus signals. the open collector healthy# output will be de-asserted. it should be actively pulled high by an external pull-up resistor (minimum 10k ? ). the next pins to mate are the i/os, and the balance of the power pins if they are not already mated. the i/os will have been pre-charged by the 1vref output. the bd_sel# pins are the last inputs to be driven to their true state. in most systems these will most likely be driven to ground when the short pins are mated. this would indicate the card is fully inserted and the power-up sequence can begin. if, however, the design is based on high availability requirements, the two pins can be ac- tively driven by the host or combined with a switch input indicating the ejector handles are fully engaged. sequencing once the proper card insertion has been assured the SMH4044 will check the status of the power enable signal from the host. this input can be used to power down individual cards on the bus via software control. it must by held high in order for the SMH4044 to enable power sequencing to the card. when these conditions have been met, the SMH4044 will drive the vgate3 and vgate5 outputs to turn on the external 3 volt and 5 volt power fets. the slew rate of these outputs is controlled to 250v/s. different slew rates can be accommodated by either adding an additional capacitor between the mosfet gate and ground or by injecting current into the islew input. all circuitry on the card is held in a reset condition until the 5v (or 3.3v) supply is stable and the reset interval timer has timed out. at this point, the reset signals are de-asserted, and proper operation of the card commences. see figure 1, table 1, and flow chart 1. the SMH4044 will monitor the cards backend voltages. once they are at or above the card v trip levels the SMH4044 will drive the healthy# output low. card removal process the card removal process operates in the opposite sequence. for non-high-availability cards the action of card removal disconnects the bd_sel# (short pins) from ground and the SMH4044 will instantly shutdown the vgate outputs, change the healthy# status, and assert the local_pci_rst and local_pci_rst# outputs. because connectors to the host backplane employ stag- gered pins, power will still be applied to the SMH4044 and the i/o interface circuits. the local_pci_rst and local_pci_rst# signals will place the interface cir- cuits into a high impedance condition. the pre-charge voltage will be applied to the i/os enabling a graceful disengagement from the active bus. once the i/o pins are free of the backplane, power can be removed from the SMH4044 and other early power devices by releasing the long pins. the removal process is slightly different for a high- availability system. as the ejector handle is rotated the ejector switch will open, causing a change of state that will activate the enum# signal to the host. in response to this notification the host will de-assert a hardware controlled bd_sel# signal. this action will turn on an indicator led on the card, notifying the operator it is now safe to proceed with the removal of the card. the sequence will then follow that outlined for the non-high-availability removal pro- cess. power configurations the SMH4044 can be used in 5v only, 3.3v-only and mixed voltage systems. for systems with a single power supply, connect v cc and hst_3v_mon together to the bus power line. also connect card_3v_mon and card_5v_mon together to the card side power. now the state of vsel determines the reset level that will be used to signal valid power. for 3.3v systems tie vsel to v cc , for 5v systems tie vsel to ground.
10 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary table 1. card insertion timing figure 1. card insertion timing diagram 2057 table01 l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. p y t. x a ms t i n u t d p t v v p i r t y a l e d n w o d r e w o p o t15s t r t v v p i r t y a l e d t u p t u o t e s e r o t15s t r p l r p # t s r _ i c p _ l a c o l o t # t s r _ i c p 1 . 01s t w e l s e t a r w e l s 0 5 2s / v t e s h y a l e d n o r e w o p o t # l e s _ d b n o i t a r u g i f n o c s m 5 20 25 20 3s m n o i t a r u g i f n o c s m 0 50 40 50 6s m n o i t a r u g i f n o c s m 0 0 10 80 0 10 2 1s m n o i t a r u g i f n o c s m 0 0 20 6 10 0 20 4 2s m t t s r u p h t d i w e s l u p t e s e r n o i t a r u g i f n o c s m 5 20 25 20 3s m n o i t a r u g i f n o c s m 0 50 40 50 6s m n o i t a r u g i f n o c s m 0 0 10 80 0 10 2 1s m n o i t a r u g i f n o c s m 0 0 20 6 10 0 20 4 2s m t d w n o i t a r u d r e m i t g o d h c t a w n o i t a r u g i f n o c s 8 . 04 6 . 08 . 06 9 . 0s n o i t a r u g i f n o c s 6 . 18 2 . 16 . 12 9 . 1s n o i t a r u g i f n o c s 2 . 36 5 . 22 . 34 8 . 3s t h c t i l g h t d i w e s l u p n o i t c e j e r h c t i l g 0 4s n t f c o t u p t u o # t l u a f o t t n e r r u c r e v o 1s t g v c o f f o e t a g o t t n e r r u c r e v o 1s t c t b c t n a t s n o c e m i t r e k a e r b t i u c r i cg n i t a r e p o6 1s v cc & hst_3v_mon local_pci_rst# bd_sel1# & bd_sel2# vgate3 & vgate5 drvren# card_3v_mon & card_5v_mon healthy# v rvalid v trip v trip t hse t slew v ohvg t purst sgnl_vld# 2057 fig01
11 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary figure 2. sequence diagram flow chart 2057 fig02 vcc 1v assert outputs local_pci_rst & local_pci_rst# shut off signals drvren#, healthy#, sgnl_vld#, vgate3 & vgate5 monitor bd_sel1# & bd_sel2# for insertion yes high low no high low monitor vsel input level monitor host_3v_mon input level monitor v cc & host_3v_mon input level turn on signals drvren#, vgate3 & vgate5 monitor card_3v_mon & card_3v_mon: vtrip? low ok low ok turn on sgnl_vld turn on healthy# start timer t purst t purst timeout? no yes pci_rst released? no yes release resets
12 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary monitor inputs the SMH4044 has a total of 8 comparators that are used to monitor the health of the host platform supplies and the card-side (backend) voltages. in hot swap applications each supply going to the backend logic needs to be monitored at three points. the first point is at the source on the host connector, v cc and hst_3v_mon. if this voltage is not within specifi- cation the down stream sequencing of powering-on the backend logic will not proceed. the next stage (the cbi inputs) is one step closer to the backend logic to monitor the current flowing into the backend logic. this cannot exceed the specification; however, if it does, then the SMH4044 must turn off the source to the backend logic. the card_5v_mon and card_3v_mon inputs are used to sense the actual voltage level in the backend logic. if either comparator detects a low voltage condition the backend logic will be placed in a reset condition (local_pci_rst and local_pci_rst# asserted), but the vgate outputs will remain active so long as the host voltage and current sense are valid. two other monitor inputs, monitor1 and monitor2, can be used as additional voltage sensors on either the host side or the card side. when either or both of these monitor inputs are used on the host side, their status will be logically anded with the v cc and hst_3v_mon logic. when either or both are configured to be used as card side monitors, their status will be logically anded with the card_5v_mon and card_3v_mon logic. this allows the device to be configured in a variety of ways such as: a. 4 host side, 2 card side monitors b. 1 host side, 3 card side monitors c. 1 host side, 4 card side monitors the programmable monitor inputs are compared to the internal 1.25v reference, simplifying the monitoring of voltages higher than v cc or lower than ground. in most cases, these monitor inputs will be set to monitor an under-voltage condition, as are the other voltage monitors on the chip. both monitor1 and monitor2 can be configured to detect over-voltage conditions as well. watchdog timer the SMH4044 has an internal watchdog timer with a programmable watchdog interval of 0.8, 1.6 or 3.2 sec- onds. the watchdog is reset each time a valid i 2 c address command is received by the SMH4044. each time the SMH4044 generates an acknowledge on the i 2 c bus, it will reset the watchdog timer. the watchdog timer will also be reset on any cs# edge. v cc vs. hst_3v_mon the v cc input is the supply input and in a compactpci application this pin must connect to an early power pin on the host connector. the hst_3v_mon input is strictly a voltage monitoring input, not a supply input. the operating supply voltage range on the v cc pin is 2.7v to 5.5v, but it will only monitor a 5v supply. this is not an issue with a dual supply application, but in a single supply application these two pins must be shorted and vsel properly set. programmable v trip thresholds the host voltage monitors and the backend voltage monitors are programmable (by the factory) and provide a number of options to the end user. the v cc monitor v trip level can be selected for either a 5% or 10% supply with default values of 4.375v or 4.625v. the hst_3v_mon v trip level can be programmed to 2.65v, 2.8v, 2.95v or 3.1v. the card_5v_mon and card_3v_mon thresholds are set in relation to their corresponding host voltage monitor thresholds. their offset can be either 50mv or C 50mv. this allows the designer to select 50mv if they want a collapse in the backend voltage to trigger a local reset condition prior to the host supply collapsing and powering down the board without warning. alternatively they can choose C50mv to trigger a board shutdown based on the host power supply falling out of spec. also see figure 3 over-current circuit breaker the SMH4044 provides a circuit breaker function to protect against short circuit conditions or exceeding the supply limits. by placing a series resistor between the host supply and the cbi pins, the breakers will trip whenever the voltage drop across the series resistor is greater than the programmed value (25, 50, 75 or 125mv) for more than 16s. also see figure 4. monitoring the power supply health
13 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary reset control while in the power sequencing mode, the reset outputs are the last to be released. when they are released all conditions of a successful power-up sequence must have been met: 1) vcc and hst_3v_mon are at or above their respec- tive vtrip levels (monitor1 and/or monitor2 are above 1.25 v if configured as host side monitors); 2) bd_sel# inputs are low; figure 3. loss-of-voltage timing sequence figure 4. circuit breaker timing sequence 3) card_3v_mon and card_5v_mon are at or above their respective trip levels (monitor1 and/or moni- tor2 are above 1.25 v if configured as card side monitors); 4) pwr_en is high; and 5) pci_rst# is high. the pci-rst# input must be high for the reset outputs to be released. assuming all of the conditions listed above have been met and t purst has expired, a low input of greater than 40ns duration on the pci_rst# input will initiate a reset cycle. the duration of the reset cycle will be determined by the pci_rst# input. if pci_rst# low is shorter than t purst , the reset outputs will be driven active for t purst . if pci_rst# is longer than t purst the reset outputs will remain active until pci_rst# is re- leased. also see figure 5. software control and status reporting the SMH4044 features advanced software control and status reporting over the serial interface. this is accom- plished through writes and reads to a status register located at word address 02 hex , device address 1001 bin . the status register can be read any time the SMH4044 is not in a nonvolatile write cycle. all of the bits in the register are read-only except for bit 5. when read this bit indicates the state of the vgate5 and vgate3 outputs. it can also be written to a 1 to turn on the vgate5 and vgate3 outputs if the pwr_en pin is low. a write to the other bits in the status register is ignored. the status register bit assignments are as follows: bit 7: indicates the state of the healthy# output. if healthy# is low then this bit will be low. this bit is read- only. bit 6: indicates the state of the sgnl_vld# output. if sgnl_vld # is low then this bit will be low. this bit is read- only. bit 5: indicates whether vgate5 and vgate3 are on. if they are high then this bit will read high. if they are low and the pwr_en pin is low then this bit can be written high to turn them on. the bit can also be written low to turn them off but only if the pwr_en pin is low. bit 4: indicates whether the SMH4044 is in reset. if the part is in reset then the bit will read high. this bit is read- only. v cc or hst_3v_mon local_pci_rst# vgate3 & vgate5 card_3v_mon or card_5v_mon drvren# & sgnl_vld# t vtpd t vtr v trip 2057 fig03 v trip pwr_en vgate3 & vgate5 cbi_3 or cbi_5 fault# t cbtc 2057 fig04
14 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary figure 5. host-initiated reset timing bit 3: indicates the state of monitor2. if it is out of range then the bit will read high. this bit is read-only. bit 2: indicates the state of monitor1. if it is out of range then the bit will read high. this bit is read-only. bit 1: indicates the state of card_5v_mon. if it is below the trip point then the bit will read low. this bit is read-only. bit 0: indicates the state of card_3v_mon. if it is below the trip point then the bit will read low. this bit is read-only. local_pci_rst# t purst 2057 fig05 local_pci_rst pci_rst# t prlpr t purst
15 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary table 2. memory timing figure 6. memory timing 2057 table02 l o b m y sr e t e m a r a ps n o i t i d n o c. n i m. x a ms t i n u f l c s y c n e u q e r f k c o l c l c s 00 0 1z h k t w o l d o i r e p w o l k c o l c 7 . 4s t h g i h d o i r e p h g i h k c o l c 0 . 4s t f u b ) 1 ( e m i t e e r f s u bn o i s s i m s n a r t w e n e r o f e b7 . 4s t a t s : u s e m i t p u t e s n o i t i d n o c t r a t s 7 . 4s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s 0 . 4s t o t s : u s e m i t p u t e s n o i t i d n o c p o t s 7 . 4s t a a t u p t u o d i l a v o t e g d e k c o l c) n e l c y c ( a d s d i l a v o t w o l l c s3 . 05 . 3s t h d ) 1 ( e m i t d l o h t u o a t a de g n a h c a d s o t ) 1 + n e l c y c ( w o l l c s3 . 0s t r ) 1 ( e m i t e s i r a d s d n a l c s 0 0 0 1s n t f ) 1 ( e m i t l l a f a d s d n a l c s 0 0 3s n t t a d : u s ) 1 ( e m i t p u t e s n i a t a d 0 5 2s n t t a d : d h ) 1 ( e m i t d l o h n i a t a d 0s n i t) 1 ( a d s d n a l c s r e t l i f e s i o nn o i s s e r p p u s e s i o n0 0 1s n t r w e m i t e l c y c e t i r w 5s m note: (1) these values are guaranteed by design. bus interface general description the i 2 c bus is a two-way, two-line serial communication between different integrated circuits. the two lines are: a serial data line (sda) and a serial clock line (scl). all summit microelectronics parts support a 100khz clock rate, and some support the alternative 400khz clock. check table 2 for the value of f scl . the sda line must be connected to a positive supply by a pull-up resistor located on the bus. summit parts have schmitt trigger inputs on both lines. see figure 6 and table 2 for waveforms and timing on the bus. one bit of data is transferred during each clock pulse. the data must remain stable when the clock is high. t f t r t low t high t hd:sta t su:sta t buf t dh t hd:dat t su:dat t su:sto scl sda in sda out t aa 2057 fig06
16 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary start and stop conditions both data and clock lines remain high when the bus is not busy. data transfer between devices may be initiated with a start condition only when scl and sda are high. a high- to-low transition of the data line while the clock line is high is defined as a start condition. a low-to-high transition of the data line while the clock line is high is defined as a stop condition. see figure 7. protocol the protocol defines any device that sends data onto the bus as a transmitter, and any device that receives data as a receiver. the device controlling data transmission is called the master, and the controlled device is called the slave. in all cases the summit microelectronic devices are slave devices, since they never initiate any data transfers. acknowledge data is always transferred in 8-bit bytes. acknowledge (ack) is used to indicate a successful data transfer. the transmitting device will release the bus after transmitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data (see figure 8). the termination of a master read sequence is indicated by a non-acknowl- edge (nack), where the master will leave the data line high. in the case of a read from a summit part, when the last byte has been transferred to the master, the master will leave the data line high for a nack. this will cause the summit part to stop sending data, and the master will issue a stop on the clock pulse following the nack. in the case of a write to a summit part the master will send a stop on the clock pulse after the last acknowledge. this will indicate to the summit part that it should begin its internal nonvolatile write cycle. basic read and write the first byte from a master is always made up of a seven bit slave address and the read/write bit. the r/w bit tells the slave whether the master is reading data from the bus or writing data to the bus (1 = read, 0 = write). the first four of the seven address bits are called the device type identifier (dti). the dti for the SMH4044 is 1010 bin . th e next two bits are used to select one-of-four possible devices on the bus. the next bit is the block select bit. the SMH4044 will issue an acknowledge after recogniz- ing a start condition and its dti. in the read mode the SMH4044 transmits eight bits of data, then releases the sda line, and monitors the line for an acknowledge signal. if an acknowledge is detected, and no stop condition is generated by the master, the SMH4044 will continue to transmit data. if an acknowl- edge is not detected (nack), the SMH4044 will terminate further data transmission. see figure 10. in the write mode the SMH4044 receives eight bits of data, then generates an acknowledge signal. it will continue to generate acks until a stop condition is generated by the master. see figure 11. figure 9. typical master address byte transmission figure 8. acknowledge timing figure 7. i 2 c start and stop timing 2057 fig07 scl sda in start condition stop condition scl sda trans sda rec 1 2 3 8 9 ack 2057 fig08 scl sda 1 2 3 8 9 4 5 6 7 1 0 1 r/w 0 x x x ack 2057 fig09
17 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary random address read random address read operations allow the master to access any memory location in a random fashion. this operation involves a two-step process. first, the master issues a write command which includes the start condi- tion and the slave address field (with the r/w bit set to write) followed by the address of the word it is to read. this procedure sets the internal address counter of the SMH4044 to the desired address. after the word address acknowledge is received by the master, it immediately reissues a start condition followed by another slave address field with the r/w bit set to read. the SMH4044 will respond with an acknowledge and then transmit the 8 data bits stored at the addressed location. at this point the master sets sda high (nack) and generates a stop condition. the SMH4044 discontinues data transmission and reverts to its standby power mode. sequential read sequential reads can be initiated as either a current address read or a random access read. the first word is transmitted as with the other byte read modes (current address byte read or random address byte read). however, the master now responds with an acknowl- edge, indicating that it requires additional data from the SMH4044. the SMH4044 continues to output data for each acknowledge received. the master terminates the sequential read operation with a nack and issues a stop condition. during a sequential read operation the internal address counter is automatically incremented with each acknowl- edge signal. for read operations all address bits are incremented, allowing the entire array to be read using a single read command. after a count of the last memory address the address counter will rollover and the memory will continue to output data. figure 10. basic read figure 11. basic write master sda slave s t a r t 1 0 r / w 1 0 a c k xx x r xx x xx x xx a c k xx xx n a c k s t o p optional 2057 fig10 master sda slave s t a r t 1 0 r / w 1 0 a c k xx x w xx x xx x xx xx xx a c k a c k s t o p 2057 fig11
18 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary hardware for programming the end user can use the summit smx3200 programming cable and software that have been developed to operate with a standard personal computer. the programming cable interfaces directly between a pcs parallel port and the target application. the applications values are entered via an intuitive graphical user interface employing drop-down menus. after the desired settings for the application are deter- mined the software will generate a hex file that can be transferred to the target device or downloaded to summit. if it is downloaded to summit a customer part number will be assigned and the file will be used to customize the devices during the final electrical test operations. figure 12. programming hookup pin 9, 5v pin 7, 10v pin5, reserved pin3, gnd pin 1, gnd pin 10, reserved pin 8, reserved pin 6, reserved pin 4, sda pin 2, scl top view of straight 0.1" 0.1" closed side connector smx3200 interface positive supply supply return v cc gnd a0 a1 a2 sda scl 9 7 5 3 1 10 8 6 4 2 SMH4044 2057 fig12 c1 0.1f
19 2057 1.x 8/16/01 SMH4044 summit microelectronics, inc. preliminary package 48 pin tqfp package pin 1 detail "a" detail "b" b 0.007 - 0.011 (0.17 - 0.27) 0.02 (0.5) bsc 0.039 (1.00) 0.018 - 0.030 (0.45 - 0.75) 0.047 (1.2) max 0.037 - 0.041 (0.95 - 1.05) 0.004 - 0.008 (0.09 - 0.20) 0.354 (9.00) 0.276 (7.00) bsc bsc [a] [b] [b] [a] 48 pin tqfp ref. jedec ms-026 a inches (millimeters) ordering information SMH4044 f base part number package f = tqfp
20 SMH4044 2057 1.x 8/16/01 summit microelectronics, inc. preliminary notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a users specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. this document supersedes all previous versions. ? copyright 2001 summit microelectronics, inc. i 2 c is a trademark of philips corporation.

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